Graphics Processing Units (GPUs) with massive parallel processing architecture are able to leverage thread-level parallelism. Especially, with programming models like CUDA, OpenCL, such architectures become one of the most attractive platforms for handling not only graphics but also general-purpose applications (GPGPUs). In modern GPUs, caches have been introduced to deal with applications with irregular memory access patterns. However, GPU caches exhibit poor efficiency due to constraints in terms of size as well as many performance challenges such as cache contention, resulting from launching a large number of active threads in GPUs. In this paper, we propose a technique that can order memory requests to the L1 data cache in a friendly way than the baseline cache management by using a small number of simple queues. Experimental results show that our technique can improve GPU cache performance over the baseline architecture, thus improving IPC by 4.3% on average.